This is my modern electronic design topic, need to use the digital electronic technology knowledge to do, cannot use the monolithic integrated circuit or the PC machine. I hope you can tell me which chips and what devices to use, and so I'd like to tell you the whole idea. thank you very much indeed
The A and B are serial data inputs that control the data. When the A, B, any one is low, the data is forbidden, and the Q0 is low under the action of the rising edge of the clock (CLK) pulse.
Of course, 74164, 74164 for the 8 bit serial and out shift register. When the clearing terminal (CLR) is low, the output (QA-QH) is low.
When A, B has a high level, another is allowed to input data, and the rising edge under the action of determining Q0 status in CLK, that when the CLK of a rising edge, a data shift, when after the eight rising after the input of eight bit data and line the output from the output end of the QA-QH.
