Architecture analysis of bulldozer architecture
Two, the bulldozer architecture analysis of AMD "bulldozer" will use 32nmSOI technology, which makes the "bulldozer" compared to the "Magny cours Opteron processor" can increase the number of cores, 33% of the 50% increase in throughput without increasing power consumption under. With AMD before all of the processors are different is that the "bulldozer" adopted "modular design", each module contains two core processor, this is somewhat like a SMT enabled single core processor. Each core has its own integer scheduler and four proprietary pipelines, the two cores share a floating point scheduler and two 128 bit FMAC multiply accumulators. The difference is that in the K10 architecture, ALU and AGU share three pipelines (average 1.5), and the number of pipes in each core unit of the "bulldozer" increases to 4, 2 AGU proprietary, and 2 ALU proprietary. The L1 cache is also different, in the K10 architecture, each core has a 64KB L1 64KB L1 instruction cache and data cache; and the "bulldozer" each core has a 16KBL1 data cache, each module has a 64KB bidirectional L1 instruction cache, as to whether the reduced L1 cache will affect the performance remains to be seen. The two cores share the L2 cache, which shares the L3 cache between the modules and Beiqiao.
